Semiconductor Packaging

Comment

Comment by Paolo Nenzi on June 28, 2008 at 3:53am

Sorry Theodore,

I was reading my last comment. I have written "a package-spice exists", I made a typo, the intended words were: "no package-spice exists". i would have been lucky otherwise :)

Comment by Paolo Nenzi on June 27, 2008 at 1:09pm

Theodore,

You are right, most of the package design is done using CAD and FEA systems. In the group I am working we use Autocad, and Ansys for most of package physical design. The interconnect simulation is done with spice and spice like softwares, like Genesys. If you can pay, you can get Allegro, or Mentor's equivalent to perform Signal and Power Integrity analyses.

To design a package you have to deal with its mechanical and thermal characteristics, mainly x-y and z CTE, young modulus and thermal conductivity and most of the simulations are needed to understand package behavior during thermal cycling (rework, circuit opertions, etc.). We have used Surface Evolver to simulate the final shape of solder balls (this is a really nice free software) and put the simulated shape into Ansys models.

A good competitor of Ansys is Comsol, it is friendlier to the end user.

For Cray I have a nice link for you: http://lc.cray.com/ They made a simulation software for FDTD simulations that can help in understanding the EM propagation in the interconnects

Today IC packages are more than mechanical holders with interconnect subject to thermal cycling. Already passives (resitances, inductances and capacitances) are integrated or embedded into the package and in the future ESD structures may be embedded too. Co-design and communication protocols (and process flow) must be established between front-end, back-end and packaging team.

As far s I know, today a package-spice (compact models based tool for package design) exists.

On the difficulty in getting materials data, I can tell you that in the end you have to make your assumptions based on literature, data-sheet but then you have to run test on your own or asking for service to third party companies.

Sure, I will ask my contacts to join the discussion.

Comment by Theodore Omtzigt on June 22, 2008 at 6:35am

Paolo:

Do you know what the current tools of the trade are? When I think about the problem, finding the raw geometry and material properties seems to me the biggest problem, so are you aware of any extraction tools for that? I have never seen a package design tool but I have to believe that the MCMs that Cray and IBM are designing are full blown 3D systems and thus probably are designed using CAD systems. I would be good to understand what these tools are.

Secondly, do you have any contacts that are running into design problems here? If you do maybe you should ask them to join this group so that we can make some forward progress on mapping out the problems in this space.

Comment by Paolo Nenzi on June 17, 2008 at 12:20am

Semiconductor package design is today one of the limiting factors in trying to ride the "More than Moore" wave.
ICs are getting more complex, function-rich, they dissipate more power (leakage from deep submicron technologies is a significant part of total dissipating power) and they require higher speed in propagating signals among die in the same package.

If this were not enough, the trend is to reduce package dimensions (for mobile applications and personal devices), package more dice together, thus exacerbating mechanical and thermal issues. On the other hand, reducing core voltages and increasing speed poses tight constraints to the signal and power integrity engineers.

Package is an integral part of the system to be designed and sometimes a limiting factor for it.